In microelectronics integrated circuit device density is increasing at a high rate. In 1965 Moore's law predicted that the number of transistors per chip would double every 2 years, and the development of microelectronics has indeed roughly matched this prediction. However the implementation of further miniaturization of integrated circuits is costly and the ever more complex circuits require an increasing number of I/O leads, which complicates the contacting and packaging of the devices. Hence other means for getting higher device density are needed. An emerging alternative is to increase the device density per unit area by stacking devices on top of each other. Currently, stacked devices are mostly interconnected by wire bonding, which is a complex process that requires a large amount of space on the device and unnecessarily long connecting leads. Furthermore wire bonding commonly gives a fairly high resistance and can be unreliable.
A spin-off from microelectronics are microelectromechanical systems (MEMS), wherein the functionality of the microelectronic systems or technologies can be enhanced. In MEMS, integrated circuits are integrated with e.g. mechanical, chemical, biological functions, or, based on the vast knowledge of microelectronic processing, microelectromechanical systems such as accelerometers, sensors, or biochips are manufactured. Many of these microelectromechanical systems extended in all 3 dimensions in order to obtain the desired functionalities.
As in microelectronics, MEMS structures are mainly fabricated using silicon wafers as substrates, but e.g. other semiconducting materials, polymers, ceramics and glass are becoming more widely used. Accompanying the increasing interest in making 3D microelectronic and MEMS structures there is an increasing interest in making electrical interconnects between the front side and the back side of the substrates or wafers of the 3D structure, i.e. so called “through-wafer vias”. Using these, unreliable and costly wire bonding is avoided and the interconnect density can be increased. The through-wafer vias should occupy as small area as possible on the wafers and the resistance of the electrical interconnects should be low. Furthermore the processing of the through wafer vias should be compatible with conventional processing technologies in the field.
Different through-wafer via designs have been disclosed, and the strategy for making the via can be divided into two categories. In the first category the through-wafer vias are formed by the wafer material, e.g. a doped semiconductor via. In the second category a through-wafer via hole is formed in the wafer using for example laser ablation, drilling, wet etching or dry etching. Thereafter a conductive material is deposited, e.g. using a physical vapour deposition (PVD) process, on at least the sidewalls of the through-wafer via hole. To increase the cross sectional area of the conductive through-wafer via (in order to reduce the electrical resistance) a metal or metal alloy is commonly plated onto the conductive coating. Through-wafer vias of the first category generally have a relatively high resistance as compared to through-wafer vias of the second category due to the higher conductivity of the metal or metal alloy.
The technique used for the formation of the via hole mainly depends on the wafer material. However, in general the via holes extend through the wafer with vertical sidewalls. The deposition of a conductive material on the sidewalls using a line-of-sight process such as PVD is a challenging operation, particularly for holes with a high aspect ratio, since there is a shadowing effect from the edges of the via hole.
Conventional low resistance through-wafer vias in silicon are typically formed by using either wet etch processing or dry etch processing to form the via hole. Anisotropic etch processes such as KOH-etching, which is a wet etching process, or deep reactive ion etching (DRIE), which is a dry etching process, are commonly used. Using anisotropic wet etching the geometry of the via hole is restricted by the crystal planes of the wafer material and the via holes consequently occupy a relatively large area. The area can be somewhat reduced by etching from both sides of the wafer, wherein the etched recesses meet in-between the sides. However, when etched recesses meet at the opening of the via hole, other crystal planes are formed. These crystal planes are then etched and may generate areas in the middle portion of the via holes that are not in-line of sight from the opening of the via hole, i.e. these areas are shaded and can not be coated using a physical vapour deposition process. Physical vapour deposition is a line-of-sight process and only surfaces in line-of-sight from the evaporation/sputtering source will be coated. DRIE is advantageous since a via hole with vertical walls, and hence occupying a smaller area, is possible. These via holes with vertical via holes do not suffer from the shadow effect described above, but there still will be a shadowing effect due to the vertical walls, particularly for narrow and deep via holes.
Accordingly conventional low resistance through-wafer vias are formed in through wafer via holes that suffer from an incomplete coverage of the via hole by the conductive material. This limits the reliability of DRIE etched through-wafer vias, particularly for narrow vias made in thick substrates.